Memory systems of the type referred to above input data during a write cycle and usually memory cell contents are updated as soon as possible after data is input during a write cycle. In some cases it is desirable to abort the write operation before the data stored in the memory is changed but the time during which a write cycle can be safely aborted is usually very short.
The present invention provides an improved memory design and memory operation in which write cycles may be safely aborted. In a preferred embodiment a write abort signal may be provided at any time up to the start of a next memory read or write cycle.
It is a further object of the present invention to provide a improved memory design which operates with conventional read and write cycle timing but includes additional circuitry to allow write abort operations.
The invention is particularly applicable to memory designs as described in our copending U.K. Patent Application No. 9116480.6. The disclosure in that copending application is incorporated herein by cross reference.